The invention relates generally to CMOS devices, and more particularly to forming discrete p-wells for the n-type devices.
In CMOS technology, it is generally known to utilize a xe2x80x9ctwin tubxe2x80x9d process to form a discrete, p-type well region (hereafter xe2x80x9cp-wellxe2x80x9d) into which the NFET will be formed, and a discrete, n-type well region (xe2x80x9cn-wellxe2x80x9d) into which the PFET will be formed. The wells are used to more precisely control the threshold voltages of the transistors. See for example U.S. Pat. No. 5,792,680, xe2x80x9cMethod of Forming a Low Cost DRAM Cell with Self-Aligned Twin Tub CMOS Devices and a Pillar Shaped Conductor,xe2x80x9d to Sung et al. As shown in FIGS. 5A-5G of the patent, an n-well and p-well are formed using a composite imaged structure of BPSG 16 and silicon nitride 18. First the p-type dopant is implanted so that it is shallower beneath the mask structure and deeper in areas where the mask structure is absent, then the n-type dopant is implanted at an energy such that it does not implant into unmasked areas. Both implants are carried out at a concentration of 1E13 to 1E14 and an energy of 1-2 Mev.
More recently, twin tub CMOS devices have utilized so-called xe2x80x9cretrogradexe2x80x9d wells, in which the concentration of dopant is higher at the bottom of the well and lower at the upper surface of the well. This doping profile helps prevent latch up by raising the threshold voltage of the parasitic device formed by the well. An example of prior art retrograde wells is shown in FIG. 1 of U.S. Pat. No. 5,814,866. Photoresist defines a p-well region, and a sequence of implants is carried out to form first the deep, highly doped portion of the p-well (implant concentration 1E13, energy 2 Mev), then the more shallow, more lightly doped portions of the well (e.g. 1.25 Mev, 1 Mev). Note again that a p-region forms below the mask that is shallower than where the substrate is unmasked. Then arsenic ions are implanted to form the n-well, again in a sequence with decreasing energy, to form a retrograded n-well with the mask in place.
In forming twin-tub, 0.11 um lithography CMOS devices (that is, FETs with effective channel lengths less than or equal to approximately 0.11 um), the inventors found that the threshold voltages of n-type transistors within about 1.5 um of the p-well/n-well interface exhibited threshold voltage shifts of up to 80 mV. Repeated attempts to address this threshold voltage shift by altering the implant dose and/or energy proved unsuccessful. While these threshold voltage shifts could be reduced to some extent by altering doping profiles, they were not eliminated or reduced to an acceptable level (i.e. less than about 10 mV). Moreover, these solutions created new problems. The altered doping profiles decreased the efficiency of the resulting well regions. These shifts in threshold voltage could lead to catastrophic failures in the Boolean operations of the resulting logic circuits.
It is thus an object of the present invention to form twin-tub CMOS devices that do not exhibit threshold voltage shifts in devices adjacent the p-well/n-well interface.
In a first aspect, the invention comprises a method of forming the n-well and p-well regions on a substrate, comprising the steps of forming a first mask structure having a given thickness on the substrate; carrying out n-well implants into regions of the substrate exposed by the first mask structure; substantially reducing said thickness of said first mask structure; carrying out a first p-well implant through said first mask structure, so that a first implant region is formed below the n-well and a second implant region is formed below the first mask structure, the first implant region being deeper than the second implant region; forming a second mask structure on the substrate having an image generally complementary to the first mask structure; and carrying out p-well implants into regions of the substrate exposed by the second mask structure.
In a second aspect, the invention comprises a method of forming abutting retrograde n-well and p-well regions on a substrate, comprising the steps of forming the retrograde n-well by implanting with a first dopant species; and forming the retrograde p-well by first carrying out a deep implant with a second dopant species under conditions that substantially reduce scattering of said second dopant species into abutting regions of said retrograde n-well.
In a third aspect, the invention comprises a CMOS device having FETs with effective channel lengths less than or equal to approximately 0.11 um formed in adjacent, retrograde nwells and pwells, wherein threshold voltages of FETs formed with approximately 1.5 um of an interface between said nwells and pwells are constant within approximately 10 mV.